Course syllabus


EDA234 / DIT796 Digital project laboratory lp2 ht20 (7.5 hp)

Course is offered by the department of Computer Science and Engineering

Contact details

Arne Linde - examiner, lecturer and laboratory responsible

Phone :   772 1683
Office : room 4464, floor 4, EDIT building
Email :

Torbjörn Tjelldén - supervisor and laboratory responsible

Phone :   772 1197
Office : room 4464, floor 4, EDIT building
Email :





Monday 2/11  
Registration of project groups and projects.

Labb  ED4220, ED4225
(in our course lab)
Monday 2/11 15.15-17

Laboratory on Xilinx software.
Registration of projects.

Labb  ED4220, ED4225
Tuesday 3/11 

Laboratory on Xilinx software.
Registration of projects.

Programmable logic. Registration of project groups and projects.

Tuesday 5/11 
(group room 4215)

Laboratory on Xilinx software.
Registration of project groups and projects.
Tuesday 5/11  

Lecture in report writing, etc.



Vecka 3 - 8

Logical design, structure, test, modifications, documentation. 
Local: Project room:
The supervisor is available in the course laboratory or online (From Reading Week 2):

Mo  13-15
We  10-12
Fr   10-12

Other times by appointment. The supervisor assigns the laboratory site and distributes tools, components, instruments etc.

Each week, the group must have a brief meeting with the supervisor in order to determine  the work progresses. In order to get grade for the course, one are premitted to miss at most two of these meetings.


Course purpose

The course is purely project-oriented. In groups of five the students works with the conception, design, implementation and evaluation of a reasonable digital systems project of their choice.

Learning objectives and syllabus

Learning objectives:

  • describe the principles for a structured and hierarchical description of smaller digital systems [P, R].
  • describe how programmable logic circuits work and how they are best utilized [L, R, P].
  • handle electronic design automatic (EDA) tools to develop and verify programmable logic circuits [L, R, P].
  • search for information in documentation/datasheets of commercial electronic components [R, B, W].
  • implement a prototype digital system considering aspects of clocking, synchronization, and control (state machine) [R, P].
  • determine power supply requirements for digital circuits in environments with multiple voltages [R, P].
  • develop a prototype digital system, from specification, via implementation and verification, to testing and evaluation [W,B.P]

Link to the syllabus Chalmers. (Links to an external site.)
Link to the syllabus GU.

Course literature

Most of the material is available in the course lab.
However, it is good to have access to a book about VHDL.

Changes in the course.

This course is given in English

Higher requirements for weekly deliveries of working VHDL code

Course design

The course begins with some lecture and exercises that allows students to become familiar with CAD/EDA tools. Subsequently, the students themselves proceed with the construction work under supervision. The project work is performed in groups of three or four students. Each group selects a task of its own or follows a proposal from a catalog of projects. Components, instruments and equipment will be available for students in accessible premises for a period of six weeks. Construction work is presented in a written report. Students have a meeting each week with a supervisor. The course concludes with a seminar with mandatory attendance, where projects are presented.


"Examination" only takes place in connection with the examination period for reading period 4, Saturday 1 to Saturday 8 of June. Exam time is booked in Canvas. The times are available from week 8 (reading week). Each group report their work in the form of a:

a) Written report
     (submitted in Canvas no later than 2 full weekdays before the "Exam")
b) Brief written report from each group member
     about his participation in the project (max. A4)
c) Practical demonstration
d) Presentation of about 30 minutes.

In order to be approved on the course, each group member must be able to describe, in detail, the part of the construction in which he / she have participates. Each group member must have participated in some part of the design. A team member may fail the project while the others can be approved.

The grade is based on a basic grade based on the difficulty of the project. This is complemented with the result of the project prototype and the documentation.

Individual grades are then based on participation in project meetings, participation in the project and the oral presentation.

To be allowed to present report, there must be a prototype with basic functionality.

In case of failure of one the parts, re-examination is offered within one week.
Thereafter, an examination opportunity is offered in connection with the re-examination period in August.

Project groups and projects

The projects are carried out in groups of 3 to 4 students. Due to limited number of laboratory places, the number of groups can be no more than 6. The group choose the project them self, inspiration can be obtained from our old project catalog. When you know what you want to do, discuss the project with the supervisor so that he can assess whether the level of complexity is high enough or to high.

The project group are assembles based on the self estimation.
However, you have the opportunity to carry out the project with a friend.

The requirements for the project are:

The supervisor judges that an implementation require 4-10 integrated circuits.
At least one complex component that is not present on the development board must be purchased and included in the design.

If the result is a construction with lower complexity, depending on an innovative design, the result is approved. If, on the other hand, the lower complexity is achieved by the group cutting down on functionality on its own, without first discussing with the supervisor, then the project is rejected.

A control-unit clocked at least in 1MHz.

At least one programmable-logic circuit (CPLD / FPGA) used in a non-trivial manner. For the control unit, the CPLD circuits are most suitable. FPGA cards may be used, in order to achieve high project rating, at least one CPLD must be used.


  1. A block diagram must be submitted no later than Monday week 3 and approved by the supervisor no later than Friday week 3
  2. The course laboratory is not available after 5 pm on Friday, 18/12. The practical part of the projects (construction and testing) must therefore be completed before this time. Make a proper schedule of the project and work purposefully so that you do not have problems with the deadline.

Keys, responsibilities and security

The course laboratory is locked with a card lock. The project groups are responsible for their tools, instruments, etc. Make sure that the mains voltage is switched off when you leave the course laboratory. No work are premiered on parts whit net power (230 volt). It´s not allowed to repair any broken instrument. Non-functioning equipment is hand over to the supervisor. The project room is used by others so it is important that you pick up after you.

Design methodology 

Work according to the top-down principle. First, make a system specification. Divide the project into data-path  and an control-unit. Break down these blocks in sub-functions.
Some projects may be realized with a microprocessor after permission from the examiner. Write documentation continuously.


Components we have in stock are on the component list.
We order weekly from
Some special circles can make the projects trivial, thous components will not be allowed. However, we want you to choose some component on your own. Keep in mind that the delivery time for components can be long, so order only components that are in stock in Europe. The component list is available online and there are links to more information.


Course summary:

Date Details Due