Course syllabus

Course-PM

EDA284 / DIT361 EDA284 / DIT361 Parallel computer architecture lp3 VT21 (7.5 hp)

Course is offered by the department of Computer Science and Engineering

Contact details

  • Miquel Pericas <miquelp@chalmers.se> (Examiner and Lecturer)
  • Mustafa Abduljabbar <musabdu@chalmers.se> (Projects and Labs)
  • Jing Chen <chjing@chalmers.se> (Exercises and Labs)

Guest Lecturers: 

  • Bhavishya Goel and Sonia Rani (European Processor Initiative, Chalmers)
  • Yiannis Sourdis (on NoC, Chalmers) 

Student Representatives

We are still looking for student representatives for EDA284. Currently we have only two confirmed representatives:

Course purpose

 This course looks at the design of current multicore systems with an eye towards how those designs are likely to evolve over the next decade.

Preliminary Schedule

Zoom link: https://chalmers.zoom.us/j/66824528274?pwd=OTdFVitkaDB0QTk1RWlXRzh3Z3o3QT09

We will follow this schedule:

Session Date
Type
Content
Teacher
Recommended reading
Jan 19th, 9h-12h
Lecture 1
Introduction, Basic concepts, Trends, Performance metrics 
Miquel
1.3, 1.4, 1.5
Jan 20th, 8h-10h
NO SESSION
 
 
 
Jan 22nd 9h-12h
Lecture 2 
OoO, Caches, Vector Architectures 
Miquel
3.4, 3.7
Jan 26th 9h-12h
Project
Introduction to Project + Roofline Model recap
Mustafa
 
Jan 27th 8h-10h
NO SESSION
Jan 29th 9h-12h
Lecture 3 
Multiprocessor systems (I) 
Miquel
 5.4.[1-4]
Feb 2nd 9h-12h
Lecture 4
Multiprocessor systems (II)
Miquel
 5.4.[5-6], 5.5.[1-4]
Feb 3rd 8h-10h
Exercises 1
SMPs, Metrics, Vector
Jing
 
Feb 5th 9h-12h
Lecture 5
Core Multithreading
Miquel
 8.3
Feb 9th 9h-12h
Lecture 6
Chip Multiprocessors 
Miquel
 8.4
Feb 10th 8h-10h
Exercises 2
Coherence, cc-NUMA, Multithreading
Jing
 
Feb 12th 8h-12h
Lab 1
ARM-SVE
Mustafa
 
Feb 16th 10h-12h
Lecture 7
GPGPU
Miquel
 GPGPU reference
Feb 17th 8h-10h
Exercises 3
Chip Multiprocessors, GPU
Jing
 
Feb 19th 9h-12h
Lecture 8
Message Passing Hardware
Miquel
 5.3
Feb 23rd 9h-12h
Lecture 9
Synchronization + Coherence 
Miquel
 7.5, 7.3
Feb 24th 8h-10h
Lecture 10
Memory Consistency Models
Miquel
 7.4, 7.6
Feb 26th 8h-12h 
Lab 2
Scalability
Mustafa
 
March 2nd 10h-12h
Guest Lecture 1
On-Chip Networks
Yiannis
On-Chip Networks SLCA 
March 3rd 8h-10h
Exercises 4
Message Passing, Synchronization
Jing
 
March 5h 10h-12h
Guest Lecture 2
European Processor Initiative (EPI)
Bhavishya,
Sonia
 
March 9th 9h-12h
NO LECTURE
 --
March 10th 8h-10h
Q&A session
Exam preparation
Miquel, 
Mustafa
 
March 12th 8h-12h
Lab 3
Implementation of Coherence
Mustafa
 
March 20th
Written Exam
 
 
 

Not all the slots listed in TimeEdit will be used. Please check the above schedule. 

Course literature

  • Course Book
    • Parallel Computer Organization and Design, Michel Dubois, Murali Annavaram, Per Stenström, 2012
  • Additional readings will be provided during the lectures 

Course design

The content is divided into several parts:

  • a review of fundamental concepts in computer architecture
  • basic multiprocessor designs for the message passing and shared memory programming models
  • interconnection networks, an essential component in chip multiprocessors and scalable parallel computer systems
  • last years' recent transition towards chip multiprocessors (also known as "multicores"), including GPGPU
  • how to correctly support parallel algorithms in shared memory hardware (atomicity, coherence and consistency)

A common thread running through all content parts is a discussion of cost trade-offs with respect to performance, power, energy and programmability. A second unifying theme is the memory bottleneck, and the importance of efficient resource management.

The course includes three lab sessions where participants get experience with simulation toolchains, and a project in which they act as architects to design a computer system targeting a particular application. 

Changes made since the last occasion

  • A new session has been scheduled on Jan 26th to describe the project and provide a recap on the roofline.
  • The last lab has been replaced by a new lab that studies coherence implementation issues with gem5 and SLICC.
  • Some lectures have been reorganized and updated, and some less relevant topics have been removed

Learning objectives and syllabus

Learning objectives:

After completion of the course the student should be able to:
Knowledge and understanding
  • describe current approaches to parallel computing
  • explain the design principles of the hardware support for the shared memory and message passing programming models
  • describe the implementation of different models of thread-level parallelism, such as core multithreading, chip multiprocessors, many-cores or GPGPU
Competence and skills
  • implement synchronization methods for shared memory and message passing parallel computers
  • design scalable parallel software and analyze its performance
Judgement and approach
  • analyze the trade-offs of different approaches to parallel computing in terms of function, performance and cost

Link to the syllabus on Studieportalen Study plan

Link to the syllabus GU https://kursplaner.gu.se/pdf/kurs/en/dit361

Examination form

The course has three components: Labs, Written examination, and Project. 

The Labs are Pass/Fail. All lab reports need to be submitted and approved to get a Pass grade. A Pass grade in the Labs is necessary to get a Pass grade on the full course. 

Chalmers (CTH):

Both the Written Examination and the Project are graded on the scale: F, 3, 4, 5. A pass on both sub-courses is needed to get at least a 3 on the full course. The final grade for the course is determined according to the following table

Written Exam 3 3 3 4 4 4 5 5 5
Project 3 4 5 3 4 5 3 4 5
Final Grade 3 3 4 4 4 5 4 5 5

 

Gothenburg University (GU): 

Both the Written Examination and the Project are graded on the scale VG: Fail (U), Pass (G), Pass with Distinction (VG). A pass on both sub-courses is needed to get a Pass on the whole course. To get a Pass with Distinction (VG) grade on the full course, it is necessary to get a VG on both the Project and the Written Examination.