Course syllabus


EDA322 / DIT797 EDA322 / DIT797 Digital design lp3 VT21 (7.5 hp)

Course is offered by the department of Computer Science and Engineering

Contact details

Examiner: Ioannis Sourdis

Teaching Assistants: 

Guest lecturers:

  • Lars Svensson, Chalmers 
  • Jan Andresson, Gaisler

Course purpose

The course is intended to give fundamental knowledge about analysis, synthesis and optimization of combinatorial and sequential digital circuits. The course also presents the technologies used for implementing such circuits. As part of the course, the student will be introduced to a modern computer-based design tool (CAD), and learn the basics of hardware description language.


For Chalmers: A preparatory course in Fundamentals of digital systems and computers (e.g. EDA215EDA432EDA451) or similar.

For GU: To be eligible for the course students should have successfully completed the first year of the Computer Science Bachelors education (or equivalent) and the course DIT790 Fundamentals of Digital Systems and Computers (or equivalent).



Course Schedule

Course literature

Digital Design Using VHDL: A Systems Approach, 1st Edition by William J. Dally, R. Curtis Harting, Tor M. Aamodt

(Available in Cremona)

Course design

The course consists of Lectures, exercises, coding tutorials and Labs.

There are about 10 lectures describing the design of different types of digital circuits. In addition, there are 2 guest lectures, one from a Chalmers colleague (experts in ASIC circuits), and one from industry.

There are also recorded coding tutorials which provide knowledge on describing such circuits using a Hardware Description Language (VHDL). 

There are weekly Labs performed in groups of 2 students, which integrate the knowledge provided in the lectures to gradually, design and implement and prototype a simple microprocessor. There is first a lab tutorial for introducing the CAD tools used in the lab. Then, Labs 1-4 are compulsory to pass the lab and expect the students to implementing different parts of the processor, integrate the parts and verify its correct functionality. Lab 5 is optional and if completed give bonus points to the students. In Lab 5 students are expected to prototype the microprocessor to an FPGA board and run a given program on it and evaluate it in terms of performance, power and area.

Exercise sessions are carried out as follows: the teacher gives exercises to students to solve them in preparation of the exercise sessions. A subset of these exercises are solved in class. Students exchange their solutions with each other and reflect on the solution they see, solution is discussed in the class. 

Changes made since the last occasion

  • The coding tutorials are moved offline (recorded).
  • The exercise sessions are updated to match better the type of questions asked in the final exam.
  • Lab 5 changed to target a new FPGA tool and board.
  • Some of the lecture content is reduced.

Other than that, no significant changes compared to the previous versions of the course.

Learning objectives and syllabus

Learning objectives:

1. Knowledge and understanding

  • describe binary arithmetic units for addition, multiplication and division.
  • describe the different storage elements used in digital circuits (latches, flip-flops, different types of memories).
  • recognize the function and uses of Reconfigurable and ASIC technologies.
  • list the differences of various types of Finite State Machines (Mealy, Moore, synchronous Mealy).
  • recognize the basics of design for testability and the basic principles behind the testing.
  • identify and describe asynchronous sequential circuits.
  • list the factors that affect the timing, power and area of a digital circuit.

2. Skills and abilities

  • minimize a Boolean function or derive its canonical form.
  • create the design specifications of a digital circuit for a given problem.
  • measure the critical path delay of a digital circuit.
  • use VHDL to describe combinatorial and sequential circuits.
  • use modern tools to perform simulation, synthesis and implementation of a digital circuit described in VHDL.
  • create test benches for VHDL designs to validate their correct functionality.
  • use FPGA technology to implement a digital hardware design.
  • define FSM encodings and perform state minimization. 

3. Judgment and approach

  • evaluate the advantages and disadvantages of different implementation technologies (ASICs, FPGAs) for digital designs, and select one for a specific design.
  • compare different design for binary arithmetic (e.g. different adder designs).
  • critically evaluate and judge a design choice in terms of power, delay, area, and be able to select the one that fits the particular design constraints.

Link to the syllabus on Studieportalen Study plan

Link to the syllabus GU

Examination form

Description of how the examination – written examinations and other – is executed and assessed.


  • what components are included, the purpose of these, and how they contribute to the learning objectives
  • how compulsory and/or voluntary components contribute to the final grade
  • grading limits and any other requirements for all forms of examination in order to pass the course (compulsory components)
  • examination form, e.g. if the examination is conducted as a digital examination
  • time and place of examination, both written exams and other exams such as project presentations
  • aids permitted during examinations, as well as which markings, indexes and notes in aids are permitted

Do not forget to be extra clear with project assignments; what is the problem, what should be done, what is the expected result, and how should this result be reported. Details such as templates for project reports, what happens at missed deadlines etc. are extra important to include.

Course summary:

Date Details Due