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EDA284 / DIT361 EDA284 / DIT361 Parallel computer architecture lp3 VT22 (7.5 hp)

Course is offered by the department of Computer Science and Engineering

Contact details

  • Miquel Pericas <miquelp@chalmers.se> (Examiner and Lecturer)
  • Sonia Rani Gupta <soniar@chalmers.se> (Teaching Assistant) 

Guest Lecturers: 

  • Bhavishya Goel and Sonia Rani Gupta (European Processor Initiative, Chalmers)
  • Yiannis Sourdis (NoC, Chalmers) 

Student representatives

MPALG	mgoszcz2@gmail.com	Maciej Goszczycki
MPHPC	liaohaowei95@gmail.com	Haowei Liao
MPHPC	jnils@student.chalmers.se	Jonathan Nilsson
MPCSN	bennekum@student.chalmers.se	Erik Frans Herman van Bennekum

Course purpose

 This course looks at the design of parallel computing systems with an eye towards how those designs are likely to evolve over the next decade.

Schedule

Room reservations can be found in TimeEdit

The tentative schedule is as follows (L:Lecture, E: Exercise Session, P: Project session, LA: Lab session) . The current plan is to have all sessions in room ML14, except for the labs which are in room ED3507. The regular lectures will start at 9h. Labs and exercise sessions start at 8h!

Zoom link for online lectures and labs: https://chalmers.zoom.us/j/65743053683?pwd=VjZndGJlaDh0U1QvY1pXdFc4NldaUT09 

EDA284/DIT361 Schedule
Week Tuesday (9h-12h) ML14 Wednesday (8h-10h) ML14 Friday (9h-12h) ML14 Recommended Reading
1 (Jan 17-21) L1 Introduction/Metrics L1 Introduction + P1 Project Description

1.3, 1.4, 1.5, roofline
2 (Jan 24-28) P1 Roofline + L2 Metrics, OoO, Mem Hierarchy + Vector processors L3 Multiprocessors #1 3.4, 3.7,5.4.[1-4]
3 (Jan 31-Feb 4) L4 Multiprocessors #2 E1 SMPs, Metrics, Vector LA1 ARM-SVE (8:00h @ ED3507) 5.4.[5-6], 5.5.[1-4]
4 (Feb 7-11) L5 Chip Multiprocessors E2 Coherence, cc-NUMA L6 Core Multithreading

8.4, 8.3, in-depth on coherence
5 (Feb 14-18) L7 GPGPU LA2 Scalabilty (8:00h @ED3507) GPGPU reference
6 (Feb 21-25) L8 Message Passing E3 Multithreading, CMP, GPU L9 Synchronization 5.3, 7.5
7 (Feb 28-Mar 4) L10 Coherence and Consistency E4 Message Passing, Synchronization LA3 Coherence (8:00h @ ED3507) 7.3, 7.4, 7.6
8 (Mar 7-11) L11 Guest lecture #1: Networks-on Chip Exam preparation L12 Guest lecture #2: European Processor Initiative
9 (Mar 14-18) Exam (Saturday AM)

 

Course literature

  • Course Book
    • Parallel Computer Organization and Design, Michel Dubois, Murali Annavaram, Per Stenström, 2012
  • Additional readings will be provided during the lectures 

Course design

The content is divided into several parts:

  • a review of fundamental concepts in computer architecture
  • basic multiprocessor designs for the message passing and shared memory programming models
  • interconnection networks, an essential component in chip multiprocessors and scalable parallel computer systems
  • last years' recent transition towards chip multiprocessors (also known as "multicores"), including GPGPU
  • how to correctly support parallel algorithms in shared memory hardware (atomicity, coherence and consistency)

A common thread running through all content parts is a discussion of cost trade-offs with respect to performance, power, energy and programmability. A second unifying theme is the memory bottleneck, and the importance of efficient resource management.

The course includes three lab sessions where participants get experience with simulation toolchains, and a project in which they act as architects to design a computer system targeting a particular application. 

Changes made since the last occasion

  1. updated several lectures
  2. moved labs one week earlier
  3. moved project introduction to the first week

Learning objectives and syllabus

Learning objectives:

After completion of the course the student should be able to:
Knowledge and understanding
  • describe current approaches to parallel computing
  • explain the design principles of the hardware support for the shared memory and message passing programming models
  • describe the implementation of different models of thread-level parallelism, such as core multithreading, chip multiprocessors, many-cores or GPGPU
Competence and skills
  • implement synchronization methods for shared memory and message passing parallel computers
  • design scalable parallel software and analyze its performance
Judgement and approach
  • analyze the trade-offs of different approaches to parallel computing in terms of function, performance and cost

 

Link to the syllabus on Studieportalen (Chalmers): Study plan

Link to the syllabus (GU) https://kursplaner.gu.se/pdf/kurs/en/dit361

Examination form

The course has three components: Labs, Written examination, and Project. 

The Labs are Pass/Fail. All lab reports need to be submitted and approved to get a Pass grade. A Pass grade in the Labs is necessary to get a Pass grade on the full course. 

Chalmers (CTH):

Both the Written Examination and the Project are graded on the scale: F, 3, 4, 5. A pass on both sub-courses is needed to get at least a 3 on the full course. The final grade for the course is determined according to the following table

Course Grade (Chalmers)
Written Exam 3 3 3 4 4 4 5 5 5
Project 3 4 5 3 4 5 3 4 5
Final Grade 3 3 4 4 4 5 4 5 5

 

Gothenburg University (GU): 

Both the Written Examination and the Project are graded on the scale VG: Fail (U), Pass (G), Pass with Distinction (VG). A pass on both sub-courses is needed to get a Pass on the whole course. To get a Pass with Distinction (VG) grade on the full course, it is necessary to get a VG on both the Project and the Written Examination.

 

Course summary:

Date Details Due