MCC092 Introduction to integrated circuit design lp1 HT22 (7.5 hp)
Course is offered by the department of Computer Science and Engineering
Contact details (see also under People in left menu)
Examiner and lecturer: Lena Peterson
Email: lenap ”at” chalmers.se, phone: 031-772 1822, or 0706-268907
Office: room 4113 (EDIT building floor 4 V, facing Rännvägen)
Some lectures, adder exercises and some problems-of-the-week sessions: Victor Åberg
E-mail: abergv “at” chalmers.se, phone: 031-772 1707
Office: room 4452 (EDIT building floor 4V)
Some lectures and exercises: Stavros Giannakopolous
E-mail: stagia “at” chalmers.se, phone: 0767651852
Office: room 4475 (EDIT building floor 4V)
Lab sessions and postlab sessions: Siavash Mowlavi
E-mail: mowlavi "at" chalmers.se phone: 031-772 1790
Office: room 4451A (EDIT building floor 4V)
Lab teaching assistants:
Xu Wang: email@example.com
Marwan Ghamlouch: firstname.lastname@example.org
Xu and Marwan are second-year MPEES students.
Erik Ryman, former industrial PhD student, Omnisys Instruments
The overall aim of the course is to introduce the student to the field of CMOS integrated circuit design and to give some introductory training in the use of industrial Electronic Design Automation (EDA) tools and in understanding their role in the integrated circuit design flow. Technology node independent performance models for power and speed are presented, giving the student generic tools to estimate cost and performance properties in circuits of present and future CMOS technologies.
Note that sometimes the schedule in TimeEdit does not exactly correspond to the one listed in the Modules here; we may use fewer hours than listed sometimes. The teachers cannot update the times in the TimeEdit schedule themselves. We use the Canvas calendar for the detailed description of each session.
The textbook is Weste and Harris: ”Integrated Circuit Design”, 4th Edition. Unfortunately, it is currently unavailable from Pearson. However, you can buy it from some online bookstores such as Amazon UK. It is also possible to rent it as an e-book, but it seems not to work from Sweden. This book is the international edition of the more expensive hardback book ”CMOS VLSI Design” 4th edition. There is a companion web site for the book at
Some chapters are available in electronic form there.
Reading instructions for the textbook and other material are given per theme under each module. There is also a page with the compiled reading instructions (this course-PM gets too long if we put them here).
The exercises are compiled in this document: (still to be updated for 2022): MCC092_exercises_2021.pdf
Course design and organization
The course runs during study period 1 and gives 7.5 credit points. It is organized as a bottom-up sister course to the top-down organized DAT094 "Introduction to electronic system design". The course takes you from the basic building block, the MOS field effect transistor (MOSFET), through CMOS logic gates to sub-systems such as adders and data paths. You will derive technology-node–independent performance models for power and speed; those models are generic tools to estimate cost and performance properties of present and future CMOS technologies (put no longer in a far away distance).
The course is organized with weekly lectures and exercise sessions, home assignments, and one or two circuit-design tasks organized as a series of hands-on laboratory exercises using industrial electronic design automation (EDA) tools from Cadence. Most lecture topics have accompanying movies that we expect you to watch before the lectures. Each laboratory session is associated with a pre-lab home assignment, the on-time submission of which before the lab session is a prerequisite for being allowed to the lab hall (physically or electronically).
Scheduled times and activities
Time Activity Week/Room
Mondays 8-11.45AM Labs group 1 study weeks 3-6 in room 4220
Mondays 1.15-5PM Labs group 2 study weeks 3-6 in room 4220
Tuesdays 1.15-4(5)PM Lecture/tutorial study weeks 1-8 - in room EB and the E-studio once
Thursdays 1.15-5PM Lecture + problem of the week session study weeks 1-8 in room EB except in the E studio once
Friday 13.15-15.00 Lecture study week 1 only - in ES52
We will let you know of any changes to the schedule here in Canvas.
For each theme there will be a "problem-of the-week" session, which is on Thursdays 15.15-17.00, except for the adder theme, where it is on the Tuesday of study week 8. In that session the teacher will solve some problems from MCC092 Exercises 2022 with your input. Which problems that are to be solved is specified in each Theme module here in Canvas. Before the POTW session we expect you to have read through the specified problems and have thought through how to solve them.
See more info for each of the eight themes under "Modules".
Home assignment problem sets & pre-lab preparations
There will be three home assignment problem sets, the first of which is a quiz, and a pre-lab preparation for each of the four labs: all in all six solution sets to hand in and one quiz to answer. You must hand in your solutions no later than the deadlines shown in the table below. All submissions are individual because they are an integral part of the assessment in the course. You may work together with one other student when you complete the problem sets but each of you must write and hand in your own solution. If you worked with another student this way, that person must be identified on your submitted solution. You must be able to explain your solution at our request. If we detect deficiencies in your solutions you get a return and you will have revise and resubmit.
The lab sessions run in study weeks 3-6. They will take place in the CSE dept’s lab rooms 4220 on floor 4 in the EDIT building. On the Friday before the first lay there will be a session in lab 4225 where we make sure that the VNC setup works correctly.
The labs are to be performed in groups of two students, so called lab pairs. The teachers will decide who gets assigned to which session and on the lab pairs. The groups will be posted on the course web page no later than by Friday night in study week 2. The labs are compulsory. If you fall ill and cannot complete the lab as planned, or if other unforeseen things happen to you very late, please send a text message or an e-mail message to Lena and Siavash.
In the labs you will use Cadence tools for schematic entry and simulation. The tools are made available to you through university contract with Cadence. These tools run under Linux and can only be run on a special server, due to the contract requirements, and therefore they are not available to run on your own computers. However, when you are at Chalmers (or are logged into Chalmers via VPN) it is possible to run the tools on this server. How to run the tools are explained in the lab-memos and related documents.
Note! If you have not submitted your pre-lab assignment on time, you will not be allowed to do the lab.
Submissions, feedback, returns and re-submissions
You should always write down your own solution! Include enough of your calculations so that we can understand how you arrived at your results. You are not allowed to copy other students’ solutions, even though you are allowed to work on the problems with one other student. That one other student should be identified in your submission. You must be able to explain your solution at our request.
Submit all your solutions to home-assignment problems and pre-lab assignments via Canvas. Only submissions through Canvas will be considered since we are several teachers who cooperate on grading and giving feedback. E-mail submission is allowed only if there is a problem with Canvas.
Submit your solutions as pdf files. If your hand-in solution comprises more than one file, you can zip them into one file; it is also possible to submit first one file and then another one in PingPong. However, we prefer if you merge your separate pdf files into one file (with the pages in the right order) if possible.
Make your submissions readable. We prefer typed solutions since they are easier to read; however we accept hand-written solutions that have been scanned or photographed into a pdf file. If you write by hand, you have to write legibly so we can read it. If you take photos of your hand-written solutions make sure the photos are clear enough for the text to be read.
1 Quiz 1 (replaces hand-in set 1) Mon Sept 5 11.59PM (midnight)
2 Pre-lab 1 Fri Sept 9 1PM
3 Pre-lab 2 Fri Sept 16 1PM
4 Pre-lab 3 Fri Sept 23 1PM
5 Pre-lab 4 Fri Sept 30 1PM
6 Hand-in set 2 Mon Oct 10 11.59PM (midnight)
7 Hand-in set 3 Mon Oct 17 11.59PM (midnight)
See also the Canvas assignments at the bottom of this page. The deadlines there should be the same as the ones above.
We will give feedback on your submission in Canvas: your submission will either be approved or rejected; if rejected you must revise it and resubmitted in Canvas for approval. The feedback will say which of the tasks you need to resubmit. You should resubmit in the same assignment in Canvas.
If you submit your pre-lab assignments on time, we shall give you feedback no later than at the beginning of your Monday lab session. For solutions to home-assignment problem sets that you hand in on Mondays, you shall receive feedback no later than by the start of the lecture on the following Thursday. You can follow your progress in Canvas. You will be able to see if you passed or if you got a return and have to revise, as well as the number of bonus points you have received.
If you get a return, we want your resubmission within one week from when you received our feedback. The final deadline for any resubmissions or late submissions that are to be included in the examination for period 1 2022 is Friday November 18 (that is, about three weeks after the exam). After that we will not grade any re-submissions until the re-sit exam period in January 2023, unless there are special circumstances such as illness.
Changes made since last year
- The main thing is that we have changed CMOS process from 65 nm to 45 nm. That change caused a change in server also, so many other documents also had to be updated. Quite a few minor changes here and there have also been done.
- We have also updated and simplified the adder excel exercises.
Learning objectives and syllabus
After completion of the course the student should be able to
- design static CMOS logic gates (pull-up and pull-down networks) and implement these as standard cells.
- from simple MOS transistor models, estimate static and dynamic properties of CMOS inverters and use these properties to model more complex gates.
- derive logical-effort normalized-delay parameters from circuit diagrams or layout, and use these parameters to estimate and trade off performance measures such as critical-path delays and power dissipation in present and future CMOS technologies.
- find critical paths in more complex combinatorial circuits, such as adders, and determine and minimise their delays.
- analyse wire-delay-dominated cases such as clock distribution and global interconnect, and suggest suitable buffering schemes to minimize delay or delay spread.
- design simple sequential systems that meet set-up and hold time constraints for timing circuits, including the effect of metastability in synchronisation.
- use industrial-type design automation tools to design, implement and verify basic CMOS circuit elements following the design flow supported by such tools.
- Introduction to CMOS integrated circuit design; basic building blocks, technology platforms and design tools.
- Introduction to the circuit design flow: schematic capture, circuit simulation, layout, rule checking, and layout-vs-schematic verification. Hands-on design skill training using industrial electronic design automation (EDA) tools.
- The MOSFET as a digital switch. The square-law model.
- The inverter as the basic digital and analog building block
- Static properties - the voltage transfer characteristics, switching voltage, noise margins.
- Dynamic properties - the RC delay model, buffer sizing, process corners.
- Dynamic switching power and static leakage power.
- Static CMOS logic gates. Designing logic gates with pull-up and pull-down networks.
- The two-port as a dynamic switching model. Input load capacitances and output driving capability.
- Technology independent delay measures. Definition of logical effort, parasitic delay and electrical effort (fanout).
- Critical path delays. Sizing gates for minimum path delay.
- Basic layout using standard-cell layout templates.
- The adder as a design demonstrator. Ripple carry, carry look-ahead, and prefix-tree adders.
- Interconnect and wire delay. The RC two-port wire model. Elmore's delay model. Repeaters.
- Latches and flip-flops. Set-up and hold time requirements. Metastability.
- Static and dynamic power consumption. Power and clock distribution. Power gating. Clock gating.
These parts are taken from the syllabus:
The course’s 7.5 credits are divided into three course elements (Sw. kursmoment):
What you have to do to earn these credits
0111 Written examination
Pass the final exam
Pass the four pre-lab problem sets and pass the four in-lab sessions
0311 Home assignments
Pass the three home-assignment problem sets (where the first one is now a quiz)
The examination is designed to encourage you to work continuously throughout the course with the material, since we know that it is hard to grasp the contents otherwise. The prelabs are there to make sure you get the most learning from the in-lab sessions. All tasks are individual since you have quite varying knowledge at the start of the course. However, you will work in pairs in the lab (as explained in more detail above).
Your grade is determined by the final exam (for details, see below).
The final exam
The final exam is a five-hour exam. It is a closed-book exam, but you are allowed to bring one A4 page of hand-written notes (you can write on both sides). You are also allowed to bring a calculator.
The exam comprises six problems with total maximum score of 60 points. You need at least 50 points to earn the grade 5, 40 points for the grade 4 and 30 points for the grade 3, which is the grade required to pass. If you have less than 30 points you fail the exam (usually recorded as U in the grading records). Any bonus points (see below) will be added to your score before the resulting higher grade is determined once you have reached 30 points on the exam. So, bonus points can give you a higher grade, but cannot be used to pass the course.
Note that you have to sign up for the exam! If you have not signed up you will not be allowed to take the exam.
Good hand-in problem-set and prelab solutions submitted on time will earn you bonus points - one point per hand-in and pre-lab problem set. All in all, you can earn seven bonus points. To earn you a bonus point, a hand-in or prelab problem-set solution must be
- handed in on time
- legibly written
- comprehensible (that is, we must understand what you mean)
- substantially correct (that is only minor mistakes that do not require resubmission)
Your submissions should be written in English. For the quiz that replaces hand-in problem set 1, one bonus point will be allotted for results that are 75% correct or higher (that is, at least 16 out of 22 marks). You are only allowed to take the quiz once for the bonus point.
A 7.5-credit course is to correspond to 1/8 of an academic year, that is to a work load of 1600/8=200 hours. During the nine weeks of a study period this corresponds to 22 hours a week. Hence, with two courses running in parallel the nominal workload is 44 hours/week. The time scheduled for this course is 69 hours, 16 hrs. for lab sessions and 53 hrs. for lectures and exercises. Estimated time for the seven home assignments and prelabs are 35 hours (5 hrs/assignment, but some may take longer depending on your background). The remaining around 100 hours are allotted for self-studies, reading the textbook, etc. That means that in addition to home assignments we expect you to work around 12 hours per week on your own.
The syllabus page shows a table-oriented view of course schedule and basics of course grading. You can add any other comments, notes or thoughts you have about the course structure, course policies or anything else.
To add some comments, click the 'Edit' link at the top.