Course syllabus

Course-PM

EDA322 / DIT797 EDA322 / DIT797 Digital design lp3 VT24 (7.5 hp)

This course is offered by the Department of Computer Science and Engineering

Contact details

Examiner: Ioannis Sourdis

Important note-1: For queries regarding the course please post your questions as a discussion thread in the Canvas course page. In case it is a private query, you can send a direct message through Canvas to both Ahsen Ejaz and I. Sourdis.

Important note-2: due to parental leave expected sometime early in SP3 (dates unknown at the moment), I. Sourdis will be replaced (for 2-3 weeks) by Ahsen Ejaz, email: ahsen@chalmers.se . During that period all regular lectures will be performed in flipped classroom style (using the lecture recordings on Canvas complimented by QA sessions in the class). Any scheduled guest lectures in the same period will be performed in class. 

Teaching Assistants: 

Guest lecturers:

  • Lars Svensson, Chalmers 
  • Jan Andresson, Gaisler

Course purpose

The course is intended to give fundamental knowledge about analysis, synthesis and optimization of combinatorial and sequential digital circuits. The course also presents the technologies used for implementing such circuits. As part of the course, the student will be introduced to a modern computer-based design tool (CAD), and learn the basics of hardware description language.

Prerequisites

For Chalmers: A preparatory course in Fundamentals of digital systems and computers (e.g. EDA215, EDA432, EDA452) or similar.

For GU: To be eligible for the course students should have successfully completed the first year of the Computer Science Bachelors education (or equivalent) and the course DIT790 Fundamentals of Digital Systems and Computers (or equivalent).

Schedule

 

TimeEdit (we will not use all the time slots in TimeEdit, please look at the link below for the slots we will use)

Course Schedule

Course literature

Digital Design Using VHDL: A Systems Approach, 1st Edition by William J. Dally, R. Curtis Harting, Tor M. Aamodt

(Available in Cremona)

Course design

The course consists of Lectures, exercises, coding tutorials and Labs.

There are about 10 lectures describing the design of different types of digital circuits. In addition, there are 2 guest lectures, one from a Chalmers colleague (experts in ASIC circuits), and one from industry.

There are also recorded coding tutorials which provide knowledge on describing such circuits using a Hardware Description Language (VHDL). 

There are weekly Labs performed in groups of 2 students, which integrate the knowledge provided in the lectures to gradually design, implement and prototype a simple microprocessor. There is first a lab tutorial for introducing the CAD tools used in the lab. Then, Labs 1-4 are compulsory to pass the lab and expect the students to implement different parts of the processor, integrate the parts and verify its correct functionality. Lab 5 is optional and if completed give bonus points to the students. In Lab 5 students are expected to prototype the microprocessor to an FPGA board and run a given program on it and evaluate it in terms of performance, power and area.

Exercise sessions are carried out as follows: the teacher gives exercises to students to solve them in preparation of the exercise sessions. A subset of these exercises are solved in class. Students exchange their solutions with each other and reflect on the solution they see, solution is discussed in the class. 

Changes made since the last occasion

  • The coding tutorials are moved offline (recorded).
  • The exercise sessions are updated to match better the type of questions asked in the final exam.
  • Lab 5 changed to target a new FPGA tool and board.
  • Some of the lecture content is reduced.

Other than that, no significant changes compared to the previous versions of the course.

Learning objectives and syllabus

Learning objectives:

1. Knowledge and understanding

  • describe binary arithmetic units for addition, multiplication and division.
  • describe the different storage elements used in digital circuits (latches, flip-flops, different types of memories).
  • recognize the function and uses of Reconfigurable and ASIC technologies.
  • list the differences of various types of Finite State Machines (Mealy, Moore, synchronous Mealy).
  • recognize the basics of design for testability and the basic principles behind the testing.
  • identify and describe asynchronous sequential circuits.
  • list the factors that affect the timing, power and area of a digital circuit.

2. Skills and abilities

  • minimize a Boolean function or derive its canonical form.
  • create the design specifications of a digital circuit for a given problem.
  • measure the critical path delay of a digital circuit.
  • use VHDL to describe combinatorial and sequential circuits.
  • use modern tools to perform simulation, synthesis and implementation of a digital circuit described in VHDL.
  • create test benches for VHDL designs to validate their correct functionality.
  • use FPGA technology to implement a digital hardware design.
  • define FSM encodings and perform state minimization. 

3. Judgment and approach

  • evaluate the advantages and disadvantages of different implementation technologies (ASICs, FPGAs) for digital designs, and select one for a specific design.
  • compare different designs for binary arithmetic (e.g. different adder designs).
  • critically evaluate and judge a design choice in terms of power, delay, area, and be able to select the one that fits the particular design constraints.

Link to the syllabus on Studieportalen Study plan

Link to the syllabus GU https://kursplaner.gu.se/pdf/kurs/en/dit797

Examination form

The course is examined by an individual final written exam given and by 4 laboratory assignments.

The final exam is 4 hours-long  and is normally written in an examination hall with closed books (1 A4 paper sheet, i.e., up to 2 pages, of notes are allowed). Many exam questions will follow the style of the exercises in the exercise sessions; more information about the exam questions can be found here: Examination information. The final exam covers the activities in the lectures and exercise sessions of the course.

The Laboratory work is carried out in groups of normally 2 students and examined at the laboratory. A 5th voluntary lab assignment contributes an extra 6% grade to the exam grade. Delivering within the deadline for each of the first 4 lab assignments contributes an extra 1% grade to the exam grade each (4% in total). Passing the lab part of the course requires passing the compulsory assignments and passing a final lab exam which covers all lab assignments. 

Both passing the laboratory part of the course and the final exam are required for passing the course. In that case, the exam grade defines the course grade.

The grading scale comprises for Chalmers fail, 3, 4, 5 and for GU Fail (U), Pass (G), Pass with Distinction (VG).