Course syllabus

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EDA322 / DIT797 Digital design lp3 VT20 (7.5 hp)

Course is offered by the department of Computer Science and Engineering

Contact details

Examiner: Ioannis Sourdis

Teaching Assistants: 

Guest lecturers:

  • Lars Svensson, Chalmers 
  • Jan Andresson, Gaisler

Course purpose

The course is intended to give fundamental knowledge about analysis, synthesis and optimization of combinatorial and sequential digital circuits. The course also presents the technologies used for implementing such circuits. As part of the course, the student will be introduced to a modern computer-based design tool (CAD), and learn the basics of hardware description language.

Prerequisites

For Chalmers: A preparatory course in Fundamentals of digital systems and computers (e.g. EDA215, EDA432, EDA451) or similar.

For GU: To be eligible for the course students should have successfully completed the first year of the Computer Science Bachelors education (or equivalent) and the course DIT790 Fundamentals of Digital Systems and Computers (or equivalent).

Schedule

Course Schedule

TimeEdit

Course literature

Digital Design Using VHDL: A Systems Approach, 1st Edition by William J. Dally, R. Curtis Harting, Tor M. Aamodt

(Available in Cremona)

Course design

The course consists mainly of Lectures and Labs, and in addition a weekly of exercise sessions (2 hour/week).

There are 19 lectures of two types (roughly 2-3 per week): (i) lectures describing the design of different types of digital circuits, and (ii) lectures providing knowledge on describing such circuits using a Hardware Description Language (VHDL). Moreover there are 3 guest lectures, two from Chalmers colleagues (experts in ASIC and Asynchronous circuits), and one from industry.

There are weekly Labs performed in groups of 2 students, which integrate the knowledge provided in the lectures to gradually, design and implement and prototype a simple microprocessor. There is first a lab tutorial for introducing the CAD tools used in the lab. Then, Labs 1-4 are compulsory to pass the lab and expect the students to implementing different parts of the processor, integrate the parts and verify its correct functionality. Lab 5 is optional and if completed give bonus points to the students. In Lab 5 students are expected to prototype the microprocessor to an FPGA board and run a given program on it and evaluate it in terms of performance, power and area.

Exercise sessions are carried out as follows: the teacher gives exercises to students to solve them in preparation of the exercise sessions. A subset of these exercises are solved in class. Students exchange their solutions with each other and reflect on the solution they see, solution is discussed in the class. 

Changes made since the last occasion

No significant changes compared to the previous version of the course.

Learning objectives and syllabus

Learning objectives:

1. Knowledge and understanding

  • describe binary arithmetic units for addition, multiplication and division.
  • describe the different storage elements used in digital circuits (latches, flip-flops, different types of memories).
  • recognize the function and uses of Reconfigurable and ASIC technologies.
  • list the differences of various types of Finite State Machines (Mealy, Moore, synchronous Mealy).
  • recognize the basics of design for testability and the basic principles behind the testing.
  • identify and describe asynchronous sequential circuits.
  • list the factors that affect the timing, power and area of a digital circuit.

2. Skills and abilities

  • minimize a Boolean function or derive its canonical form.
  • create the design specifications of a digital circuit for a given problem.
  • measure the critical path delay of a digital circuit.
  • use VHDL to describe combinatorial and sequential circuits.
  • use modern tools to perform simulation, synthesis and implementation of a digital circuit described in VHDL.
  • create test benches for VHDL designs to validate their correct functionality.
  • use FPGA technology to implement a digital hardware design.
  • define FSM encodings and perform state minimization.-

3. Judgment and approach

  • evaluate the advantages and disadvantages of different implementation technologies (ASICs, FPGAs) for digital designs, and select one for a specific design.
  • compare different design for binary arithmetic (e.g. different adder designs).
  • critically evaluate and judge a design choice in terms of power, delay, area, and be able to select the one that fits the particular design constraints.

Link to the syllabus at Chalmers Study plan
Link to the syllabus at GU https://kursplaner.gu.se/pdf/kurs/en/dit797

Examination form

The course is examined by an individual 4 hour-long exam given in an examination hall (notes and books not permitted) and 5 laboratory assignments (Labs 1-4 are compulsory to pass the course).

The Laboratory work is carried out in groups of normally 2 students.

Opportunity for re-examination is given twice a year.

A student who failed a same examination twice has the right to request of the department a change of examiner. The request is to be in writing and submitted as soon as possible. The department is to grant such a request without undue delay.

In cases where a course has been discontinued or major changes have been made a student should be guaranteed at least three examination occasions (including the ordinary examination occasion) during a time of at least one year from the last time the course was given.

The grading scale comprises for Chalmers fail, 3, 4, 5 and for GU Fail (U), Pass (G), Pass with Distinction (VG).

Course summary:

Date Details Due